An FPGA-Based Singular Value Decomposition Processor
Ma Weiwei, Mary E. Kaye, Dennis Lüke, Rajamani Doraiswami · 2006
A two-sided rotation Jacobi SVD algorithm is used to compute the SVD and is implemented on a two million gate FPGA. A mesh-connected array structure is proposed based on Brent, Luk, and Van Loan's idea of an expandable square systolic array of simple 2x2 processors to compute the SVD of a large matrix, so as to shorten the iteration time and thus increase the implementation speed. The array consists of an n/2xn/2 array of 2x2 processor elements to compute the SVD of an nxn matrix. The trigonometric functions and the vector multiplication in the algorithm are tailored to the use of CORDIC (coordinate rotation digital computer) algorithms for hardware-efficient solutions. Two SVD processors, the basic SVD processor and the extended SVD processor, were developed. The algorithms to decompose the matrix were first evaluated in Matlab and then the processors were implemented using the Virtex-II FPGA from Xilinx as the target device. The basic SVD processor utilizes the proposed mesh-connected array structure and CORDIC algorithm. The implementation concentrates on utilizing the features of the FPGA to speed up operations and reduce the area required. In order to compute a large SVD without increasing the size of the FPGA, the extended SVD processor was developed to reuse the SVD array of the basic SVD processor. These two processors were successfully implemented on the FPGA device. Speed data and comparisons are presented