Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined Transceiver Designs
Jyh-Ting Lai, An-Yeu Andy Wu, Chien-Hsiung Lee · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2007
Traditional approaches of automatic gain control (AGC) involve estimating the average power or the peak amplitude over an extended time period, which results in high hardware complexity and a long processing time. Moreover, the accuracy of traditional approaches is seriously degraded by noise and intersymbol interference. In this paper, we propose a joint AGC and equalization (Joint AGC-EQ) scheme, in which the AGC circuitry comprises only one-tenth of the area of a traditional AGC. In addition, the total convergence time of the proposed Joint AGC-EQ is only half that of traditional blind equalization. The scheme is already silicon proven for the application of a Fast Ethernet transceiver using Faraday/UMC 0.18-mum cell libraries