Power-complexity analysis of pipelined VLSI FFT architectures for low energy wireless communication applications
Sangjin Hong, Suhwan Kim, Marios C. Papaefthymiou, W.E. Stark · 2003
Large fixed-throughput fast Fourier transform (FFT) modules are used in multi-carrier spread spectrum receiver design for demodulation and synchronization. The power dissipation of an FFT module depends highly on the number of processing units and their interconnect topology. This paper analyzes the energy dissipation and complexity of a pipelined parallel FFT architecture. Optimum design choices are presented for the degree of spatial parallelism and temporal multiplexing. Simulation results are obtained using EPOCH and HSPICE with 0.35 /spl mu/m standard CMOS technology.