Tradeoffs in supporting two page sizes
Madhusudhan Talluri, Shing I. Kong, Mark D. Hill, David A. Patterson · 1992
As computer system main memories get larger and processor cycles-per-instruction (CPIs) get smaller, the time spent in handling translation lookaside buffer (TLB) misses could become a performance bottleneck. We explore relieving this bottleneck by (a) increasing the page size and (b) supporting two page sizes.