The architecture and applications of the motorola DSP56000 digital signal processor family
K.L. Kloker · 2005
This paper describes the architecture and applications of the DSP56001, a RAM-based member of the Motorola DSP56000 family of high performance, user-programmable CMOS digital signal processors. The DSP56001 has 512 × 24 bits of program RAM and special on-chip bootstrap hardware to download user programs from an external memory or host processor. The DSP56001 also contains two 256 × 24 bit data RAM's and two 256 × 24 bit ROM lookup tables for Mu-law/A-law to linear data conversion and sine/cosine functions. The processor architecture and instruction set are highly parallel, executing 10.25 million instructions per second with a 20.5 MHz clock. Fixed point arithmetic is performed by a 24 × 24 bit, non-pipelined multiply-accumulator with 56 bit product accumulation. Extensive I/O capability is provided by a full-speed memory expansion port, a byte-wide host processor interface, an asynchronous serial communications interface and a time division multiplexed, synchronous serial interface.