An on-chip learning neural network
G. M. Bo, Daniele D. Caviglia, Maurizio Valle · 2000
We present and discuss the major results of our research activity aimed to the analog VLSI implementation of on-chip learning neural networks. In particular we present the SLANP (self learning neural processor) chip results. The SLANP architecture implements an on-chip learning multilayer perceptron network. The learning algorithm is based on the back propagation but it exhibits increased capabilities due to the local learning rate management. A prototype chip has been designed and fabricated in a CMOS 0.7 /spl mu/m minimum channel length technology. The experimental results confirm the functionality of the chip and the soundness of the approach. The SLANP performance compares favorably with that reported in the literature.