A high-speed scalable shift-register based on-chip serial communication design for soc applications
I‐Chyn Wey, You-Gang Chen, Chia-Tsun Wu, Wei Wang, An-Yeu Andy Wu · Research in Microelectronics and Electronics, 2005 PhD · 2005
In this paper, a high-speed, scalable on-chip serial transmission design is proposed to provide 2Gb/s transmission bandwidth for SoC applications. By using the dynamic control technology and the single-phase pulse-triggered TSPC shift register design, we can provide high-speed on-chip serial transmission. Moreover, the shift register design is a scalable design. By using the proposed method, we can provide 3 times wider bandwidth as compared to the prior art design (Kimura et al., 2003).