Self-test scheduling with bounded test execution time
Albrecht P. Stroele · 1992
Complex VLSI circuits with built-in self-test resources are segmented into a number of subcircuits, that to some extent can be tested concurrently. For each subcircuit a signature is collected. The test schedule has to organize the test execution such that the available resources are optimally utilized. Whereas known test scheduling methods aim at a short test execution time, or alternatively at a minimal test hardware overhead, this paper investigates the tradeoff between test time and test hardware. Test schedules are constructed that proceed within a user-specified time bound and obtain a given fault coverage with hardware cost as small as possible. This aim is reached by utilizing the mutual influence of signatures during the test execution. The result is a significant reduction of the amount of hardware required to implement a built-in selftest.