Temporal partitioning combined with design space exploration for latency minimization of run-time reconfigured designs
Meenakshi Kaul, Ranga R. Vemuri · 1999
We present combined temporal partitioning and design space exploration techniques for synthesizing behavioral specifications for run-time reconfigurable processors. Design space exploration involves selecting a design point for each task from a set of design points for that task to achieve latency minimization of partitioned solutions. We present an iterative search procedure that uses a core ILP (Integer Linear Programming) technique, to obtain constraint satisfying solutions. The search procedure explores different regions of the design space while accomplishing combined partitioning and design space exploration. A case study of the DCT (Discrete Cosine Transform) demonstrates the effectiveness of our approach. 1 Introduction Run-time reconfigurable processors [12, 22] are becoming increasingly viable with the advent of modern fieldprogrammable devices. Run-time reconfiguration allows large circuits to be implemented by multiple configurations of the same processor. This necessitat...