Design of An On-Chip Test Pattern Generator Without Prohibited Pattern Set (PPS)
Niloy Ganguly, Biplab Kumar Sikdar, P.P. Chaudhuri · 2002
Abstract | This paper reports the design of a T est P atternGenerator (TPG) for V LSI circuits. The on-chip TPG is so designed that it generates test patterns while avoiding generation of a given Prohibited Pattern Set (PPS). The design ensures desired pseudo-random qualit y of the test patterns generated.The experimental results conrm high quality of randomness while ensur-ing fault coverage close to the gures achieved with a typical Pseudo Random Pattern Generator (PRPG) de-signed around maximal length LFSR=CA. Compared to the conventional PRPG it incurs no additional cost. I.