A high-speed 8*8-bit CMOS parallel array processor
K.-K. Lee, R.G. Deshmukh · 2003
The authors present an architecture for an 8-b*8-b real-time parallel array processor that can be used for high-speed digital signal processing applications. The processor generates 18-b outputs from a stream of 8-b input data and a set of 8-b predetermined coefficients. The processor has been designed in 1.5- mu m CMOS technology, analyzed for its timing, and functionally simulated by a hardware description language and a schematic simulator. The processor includes a pipelined array of multiplier-accumulators which provides parallel operation to the processor. The processor does not use parallel operation for an input rate lower than 28.5 Msamples/s, but the degree of parallelism was increased up to three for an input rate higher than 57.0 Msamples/s. This increase of the degree of parallelism resulted in a maximum throughput of 60.2 Msamples/s.>