IDDQ testing on a custom automotive IC
S.R. Mallarapu, A.J. Hoffman · IEEE Journal of Solid-State Circuits · 1995
This paper describes the implementation of IDDQ testing combined with high voltage testing on a CMOS custom automotive IC. Special design considerations to accommodate IDDQ testing are discussed in this paper. IDDQ pattern generation, data collection and limit setting are presented. IDDQ patterns developed for this IC, together with the fault-graded patterns, achieved a higher fault coverage compared to the conventional single stuck-at-fault approach alone. The combination of the IDDQ test and the voltage screen test resulted in a higher reliability of the device.>