Video DSP architecture for MPEG2 codec
Takashi Araki, M. Toyokura, Tetsuya Akiyama, H. Takeno, B. Wilson, Kunitoshi Aono · 2002
We developed a DSP named VDSP2 (Video Digital Signal Processor version 2) for MPEG2 video coding and decoding. In order to obtain the necessary performance, we employed a 2-level parallel processing scheme consisting of a pipeline processing at the macro block level and a parallel vector processing using a SIMD configuration at the block level. In the VDSP2, we included a DSP core which execute 4 parallel vector operations and scalar operations, a DRAM controller, a DCT/IDCT circuit, a VLC/VLD circuit including a programmable controller and a data communication circuit. As a result, the real-time encoder specified in MPEG2 can be realized with two VDSP2 chips, and the decoder can be realized with one VDSP2 chip.>