High-speed architecture for Advanced Encryption Standard Algorithm
Rashmi Ramesh Rachh, P. V. AnandaMohan, Basavaraj S. Anami · 2012
This paper presents high speed architecture for AES encryption. The proposed architecture uses integrated unit of encryption in which the consecutive transformations of AES are integrated into a single unit to arrive at an architecture with shorter critical path. Further reduction in critical path is achieved by applying pre-computation technique. Synthesis results using Synopsis 0.18 μm CMOS process are also provided to substantiate the claims.