Testability of AND-EXOR Based Iterative Logic Arrays
Avik Chakraborty · arXiv (Cornell University) · 2008
Iterative Logic Arrays (ILAs) are ideal as VLSI sub-systems because of their regular structure and its close resemblance with FPGAs (Field Programmable Gate Arrays). AND-EXOR based circuits are of interest in the design of very low power circuits where energy loss implied by high frequency switching is of much consideration. This paper examines the testability of AND-EXOR based Iterative Logic Arrays (ILAs). For certain ILAs it is possible to find a test set whose size remains constant irrespective of the size of the ILA, while for others it varies with array size. Former type of ILAs is known as Constant-Testable (C-Testable). It has been shown that AND-EXOR based Logic Arrays are C-Testable and size of test set is equal to number of entries in cell truth table. The test generation problem has been shown to be related to certain properties of cycles in a set of graphs derived from cell truth table. By careful analysis of these cycles an efficient test generation technique that can be easily converted to an ATPG program has been presented for both 1D and 2D ILAs. How this property of ILAs can be used for testing FPGAs has also been discussed. Keywords - C-Testable, Iterative Logic Arrays, Bijective, Test Generation, ATPG