A graphical system for hierarchical specifications and checkups of VLSI circuits
Bernd Becker, T. Burch, G�nter Hotz, D. Kiel, R. Kolla, Paul Molitor, Hans Georg Osthof, Gisela Pitsch, Uwe Sparmann · European Design Automation Conference · 1990
The two most important frontend components of the VLSI design system CADIC are presented. The first one allows graphical specification of recursively defined circuits. The other one allows the designer to navigate across the synthesized layout following the hierarchical specification to check e.g. CADIC's hierarchical optimizations or to control the outcome of test (generation) algorithms.