Defect and error tolerance in the presence of massive numbers of defects
M.A. Breuer, Sandeep K. Gupta, Terrence Mak · IEEE Design & Test of Computers · 2004
As scaling approaches the physical limits of devices, we will continue to see increasing levels of process variations, noise, and defect densities. Many applications today can tolerate certain levels of errors resulting from such factors. We introduce a new approach for error tolerance resulting in chips containing only error acceptable for such applications.