A multilevel factorization technique for pass transistor logic
Arunita Jaekel, GRAHAM A. JULLIEN, S. Bandyopadhyay · 2002
Pass transistor logic (PTL) networks have been used by many researchers to design fast, area efficient pipelined systems. Not much work has been done in the area of multilevel logic synthesis in PTL networks. In this paper, we have investigated the use of algebraic factorization techniques to synthesize multilevel PTL networks.