A proposed DDT/IDCT chip design using quaternary logic
K.W. Current · 1988
CMOS quaternary threshold logic circuits are used in the design of the instruction memory and arithmetic sections of a proposed single-chip implementation of a unified discrete cosine transform/inverse discrete cosine transform (DCT/IDCT) architecture. The chip is projected to be capable of real-time processing of 10-MHz video signals. The unified DCT/IDCT architecture is described, and the use of quaternary logic circuits is discussed. A 17.5% area savings has been achieved.>