The VLSI implementation of STONN
W.B. Wike, Dave Van den Bout, III Miller T. · 1990
A 100000-transistor digital CMOS Hopfield neural network is presented, and its performance is discussed. STONN uses space efficient stochastic logic and bitwise pipelining to achieve massive parallelism and high operational speeds. The architecture produces solutions to optimization problems with a quality equivalent to that of solutions produced by analog networks and nearly as good as those found using simulated annealing. The massively parallel nature of STONN increases its speed of convergence by orders of magnitude over uniprocessor implementations. The completely digital STONN design provides dynamically reprogrammable parameters and a practical system implementation which can be expanded using several identical chips