The hierarchical method of synthesis of large-capacity comparators with the use of programmable logic integrated circuits
В. В. Соловьев, A. A. Posrednikova · Journal of Communications Technology and Electronics · 2009
The problem of construction of large-capacity comparators from programmable logic integrated circuits (PLICs) is discussed. A method for synthesizing large-capacity comparators with hierarchical pyramidal structures is proposed. This method is compared with two known (parallel and sequential) methods and two methods of the Altera MAX+PLUS II computer-aided design program package. The results of experimental studies have shown that, in the design of 64-bit comparators, the proposed method makes it possible to decrease the implementation cost on average by a factor of 1.09 to 1.54 and increase the processing speed on average by a factor of 3.79 to 7.17, depending on the family of PLICs.