A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system
C.-H Kim, Ji‐Hyun Lee, J.B. Lee, B.S. Kim, C.S. Park, Sungho Lee, Sangyoon Lee, C.W. Park, Junki Roh, Hyoungsik Nam, D.Y. Kim, Deuk Yong Lee, Tae‐Sung Jung, H. Yoon, S.I. Cho · IEEE Journal of Solid-State Circuits · 1998
A 64-Mbit bidirectional data strobed, double-data-rate SDRAM achieves a peak bandwidth of 2.56 GByte/s on a 64-bit-channel, 256-MByte memory system at V/sub cc/=3.3 V and T=25/spl deg/C. The circuit features are: (1) a bidirectional data strobing scheme to eliminate the clock-related skews of I/O data in a multimodule system, (2) a low-power delay-locked loop having a wide range of locking frequency (40-160 MHz) with fast access time and minimal variations, and (3) a twisted data bussing architecture with minimized loading difference between I/O data paths and small chip-size overhead associated with the 2-bit prefetch operation.