A system model for feedback control and analysis of yield: A multistep process model of effective gate length, poly line width, and IV parameters
Edward A. Rietman, S.A. Whitlock, M. Beachy, A. Roy, T.L. Willingham · IEEE Transactions on Semiconductor Manufacturing · 2001
We present a large system model capable of producing Pareto charts for several yield metrics, including effective channel length, poly line width, I/sub on/ and I/sub sub/. These Pareto charts enable us to target specific processes for improvement of the yield metric(s). Our neural network model has an accuracy of 80% and can be trained with a small data set to minimize the feedback time in the control loop for the yield. The system we describe has been implemented in a Lucent Technologies microelectronics lab in Orlando, FL.