Parallel VLSI design for a real-time video-impulse noise-reduction processor
Shih‐Chang Hsia · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2003
High-quality televisions (TVs) such as improved digital TV, enhanced TV, and high-definition TV have become popular in recent years. However, impulse noise affects TV broadcasts. This paper proposes an efficient noise-removal algorithm using an adaptive digital signal-processing approach. Simulations have demonstrated that the new adaptive algorithm could efficiently reduce impulse noise even in highly corrupted images. In order to achieve real-time implementation, a cost-effective architecture is proposed using a parallel structure and pipelined processing. The proposed processor can achieve the throughput rate of 45M pixels/s using only 4k gates and two line buffers. Unlike median-filtering chips, this processor provides better filtering quality and its circuit is much less complex.