A highly reliable pyramid tree network architecture
M. Mohsin, B. Gupta · 2002
A highly fault-tolerant pyramid tree network architecture is designed and analyzed. The idea of modularity is used to ease the VLSI implementation of the architecture. It has been shown that, besides tolerating failures in the operational processing elements, the proposed design can tolerate the spare processing element failures and link failures as well. An optimal switch structure, a well-defined reconfiguration algorithm, and a VLSI layout of the proposed design are also presented. A reliability analysis is provided, and it shows a substantial increase in system reliability of the proposed fault-tolerant pyramid tree over its nonredundant counterpart.>