Split Private and Shared L2 Cache Architecture for Snooping-based CMP
Xuemei Zhao, Karl Sammut, Fangpo He, Shaowen Qin · 2007
Cache access latency and efficient usage of on-chip capacity are critical factors that affect the performance of the chip multiprocessor (CMP) architecture. In this paper, we propose a SPS2 cache architecture and cache coherence protocol for snooping-based CMP, in which each processor has both private and shared L2 cache to balance latency and capacity. Our protocol is expressed in a new state graph form, through which we prove our protocol by formal verification method. Simulation experiments shows that the SPS2 structure outperforms private L2 and shared L2 structure.