An Efficient 10GBASE-T Ethernet LDPC Decoder Design With Low Error Floors
Zhengya Zhang, Venkat Anantharam, Martin J. Wainwright, Borivoje Nikolić · IEEE Journal of Solid-State Circuits · 2010
A grouped-parallel low-density parity-check (LDPC) decoder is designed for the (2048,1723) Reed-Solomon-based LDPC (RS-LDPC) code suitable for 10GBASE-T Ethernet. A two-step decoding scheme reduces the wordlength to 4 bits while lowering the error floor to below 10$^{-14}~$BER. The proposed post-processor is conveniently integrated with the decoder, adding minimal area and power. The decoder architecture is optimized by groupings so as to localize irregular interconnects and regularize global interconnects and the overall wiring overhead is minimized. The${\hbox {5.35~mm}}^{2}$, 65 nm CMOS chip achieves a decoding throughput of 47.7 Gb/s. With scaled frequency and voltage, the chip delivers a 6.67 Gb/s throughput necessary for 10GBASE-T while dissipating 144 mW of power.