Towards verifying VHDL descriptions of processors
Laurent Arditi, Hélène Collavizza · European Design Automation Conference · 1995
We present a system for the formal verification of processors which combines a computer algebra simplification tool with an object-oriented approach. It has been successfully used for verifying the DP32 processor described in the VHDL Cookbook. A general VHDL description style for proving processors is derived from this case study.