A system-level solution to domino synthesis with 2 GHz application
B.A. Chappell, Xielin Wang, Priyadarsan Patra, Prashant Saxena, J. Vendrell, Sarthak Gupta, Srenivas Varadarajan, Wilfred Gomes, Shadhin Hussain, Harish K. Krishnamurthy, M. Venkateshmurthy, Shailendra Jain · 2003
System structure and a taped out 0.18u 2 GHz product application result are described for a domino synthesis capability that covers all aspects of domino design, from estimation to silicon-ready layout, with custom-class optimization. The described optimization flow, abstraction modes, and key cost factors deliver power-optimized, noise-correct domino performance on complex logic.