The FPGA Implementation of 128-bits AES AlgorithmBased on Four 32-bits Parallel Operation
Chi-Wu Huang, Chi-Jeng Chang, Mao-Yuan Lin, Hung-Yun Tai · 2007
A 32-bit AES implementation is proposed in small Xilinx FPGA chip (Spartan-3 XC3S200). It uses 148 slices, 11 block RAMs (BRAMs) and achieves a throughput of 647 mega bits per second ( Mbps) at 278 MHz working frequency. It achieve 3 times improvement in throughput and 3.4 times increase to the best known similar design in throughput per area and 8% smaller in slices area. An 128-bit AES implementation in FPGA (Virtex-II XC2VP20) by parallel operations of four above 32-bit AES is also presented. Comparison to state-ofart AES cores indicates that the proposed folded designed achieves 4780 Mbps and 410 slices, which outperformed the most works by 200% in throughput and requires 20% less reconfigurable area, which results over 250% improvement in throughput/slice metric.