Two 4K static 5-V RAM's
J. Schlageter, N. Jayakumar, Jens H. Kroeger, V. Sarkissian · IEEE Journal of Solid-State Circuits · 1976
This paper describes two 4096-bit, static, TTL compatible, 5 V only, MOS RAM's with worst case access times down to 200 ns and worst case power dissipations down to 370 mW. One is organized as 1K/spl times/4 and the other as 4K/spl times/1. Both devices are obtained from the same 192- by 197-mil die by a metal mask option and both are assembled in 22-pin dual-in-line packages. A novel memory status output signal is provided to allow the system designer to utilize actual memory performance rather than worst case data sheet specifications. This allows improved system benchmarks in addition to simplified timing.