A Self Testing 2 Micron CMOS Chip Set for FFT Applications
J. Fox, G. Surace, Philip Thomas, I.A. MacAulay · 1985
A chip set for high speed radix-2 FFT applications up to 512 points is described. The chip set comprises a (16+16)*(12+12) bit complex multiplier; and a 16 bit butterfly chip for data re-ordering, twiddle factor generation and butterfly arithmetic. The chips have been implemented using the Megacell design methodology on a 2 micron bulk CMOS process. Three chips implement a complex FFT butterfly with a throughput of 10MHz, and are cascadable up to 512 points. The chips feature an off-line self testing capability.