Real-time monitoring for software development and testing
K. Jundi, Donald L. Moon · 2003
Proposes a design technique for tracing and monitoring instruction execution where general-purpose registers are used as the main source for manipulating data and results within a RISC (reduced-instruction-set computer)-based microprocessor design. The R3000 MIPS processor will be used as an example of a RISC-based microprocessor target to be monitored in an embedded computer system. The design will be independent of the way the cache memory is implemented on the unit being monitored, i.e., it will monitor on-chip or off-chip cached systems.>