Architecture of a general-purpose neural signal processor
Ulrich Ramacher, J. Beichter, N. Brüls · 2002
A versatile neurocomputer architecture must absorb in silicon the elementary compute-bound algorithmic strings shared by all known neural paradigms. The digital neural signal processor MA16 was designed to execute this set of compute-bound algorithmic operations. Its architecture and the technology chosen allow for a computing power of 800 million connections per second (1 C=16 b) at a worst-case clock rate of 40 MHz. At the board level the system performance can be augmented by means of one- or two-dimensional arrays of these chips. The neural signal processor architecture was designed as an integral part of a neurocomputer system architecture which comprises a systolic array of MA16s.>