A hierarchical infrastructure for SoC test management
Alfredo Benso, Stefano Di Carlo, P. Prinetto, Y. Zorian · IEEE Design & Test of Computers · 2003
HD/sup 2/BIST - a complete hierarchical framework for BIST scheduling, data-patterns delivery, and diagnosis of complex systems - maximizes and simplifies the reuse of built-in test architectures. HD/sup 2/BIST optimizes the flexibility for chip designers in planning an overall SoC test strategy by defining a test access method that provides direct virtual access to each core of the system.