A 56-nm CMOS 99-${\hbox {mm}}^{2} $ 8-Gb Multi-Level NAND Flash Memory With 10-MB/s Program Throughput
Ken Takeuchi, Yasushi Kameda, Susumu Fujimura, Hiroyuki Otake, Koji Hosono, Hitoshi Shiga, Yoshihisa Watanabe, Takuya Futatsuyama, Yoshihiko Shindo, MASATSUGU KOJIMA, Makoto Iwai, Masanobu Shirakawa, Masayuki Ichige, K. Hatakeyama, Shin‐ichi Tanaka, Teruhiko Kamei, Jiayi Fu, Adi Cernea, Yan Jun Li, Masaaki Higashitani · IEEE Journal of Solid-State Circuits · 2007
A single 3.3-V only, 8-Gb NAND flash memory with the smallest chip to date, 98.8 mm2, has been successfully developed. This is the world's first integrated semiconductor chip fabricated with 56-nm CMOS technologies. The effective cell size including the select transistors is 0.0075 mum2per bit, which is the smallest ever reported. To decrease the chip size, a very efficient floor plan with one-sided row decoder, one-sided page buffer, and one-sided pad is introduced. As a result, an excellent 70% cell area efficiency is realized. The program throughput is drastically improved to twice as large as previously reported and comparable to binary memories. The best ever 10-MB/s programming is realized by increasing the page size from 4kB to 8kB. In addition, noise cancellation circuits and the dual VDD-line scheme realize both a small die size and a fast programming. An external page copy achieves a fast 93-ms block copy, efficiently using a 1-MB block size