A 650-MHz, IA-32 microprocessor with enhanced data streaming for graphics and video
Ramesh Senthinathan, S. Fischer, H. Rangchi, H. Yazdanmehr · IEEE Journal of Solid-State Circuits · 1999
This paper describes a new IA-32 architecture microprocessor that implements 70 additional instructions to further accelerate the performance of data-streaming applications such as three-dimensional graphics and video encode/decode. This processor is an enhancement over the previous implementation of this family through the addition of these new instructions along with circuit improvements in several key areas for higher clock frequency. The 10.17/spl times/12.10 mm/sup 2/ die contains 9.5 million transistors and is fabricated in a CMOS five-layer-metal 0.25-/spl mu/m process with a six-layer organic land grid array package using C4 interconnect technology. It has an operating range of 1.4-2.2 V and is currently running up to 650 MHz.