Exploiting hardware sharing in high-level synthesis for partial scan optimization
Sujit Kumar Dey, Miodrag Potkonjak, Rabindra K. Roy · 1993
Anew approach to high level synthesis, which simukaneouslyad-dresses testability and resource utilization, is presented. We explore the relationship between hardware sharing, loops in the synthesized data-path, and partial scan overhead. Since loops make a circuit hard-to-test a comprehensive analysis of the sources of loops in the data path, created during high level synthesis, is provided. The paper introduces the problem of breaking CDFG loops with a minimal number of scan registers. Subsequent scheduling and as-signment avoid formation of loops in the datapath by sharing the scan registers, while ensuring high resource utilization. Experimental re-sults demonstrate the effectiveness of the technique to synthesize easily testable data paths, with significantly less partial scan cost than a gate-level partial scan approach. 1