On message resequencing in computer networks
S. Chowdhury · 2003
In computer networks incorporating virtual circuits, packets of messages are delivered at the destination in the same sequence as they are received at the source. These messages may arrive at a node D out of sequence if sent from a node S with multiple links connecting it to D. Consequently, messages may be delayed at D to put them back in sequence. Assuming that each virtual circuit contributes a Poisson stream and message transmission times have exponential distribution, the author determines expressions for mean resequencing delay and average buffer lengths. He assumes that messages belonging to different virtual circuits have different mean lengths. The author considers an infinite number of links connecting S and D. Thus, the results provide an upper bound on the above metrics for nodes connected by finitely many links. The author considers both channel level and virtual circuit level resequencing and compares them.>