MPEG-2 4:2:2@HL encoder chip set
Hisayasu SATO, Hideo Ohira, M. Kazayama, Ayako Harada, Masahiko Yoshimoto, O. Tanno, Satoshi Kumaki, K. Ishibara, A. Hanami, T. Mutsumura · 2002
An MPEG-2 4:2:2@HL encoder chip set will be presented. It is composed of an encoder LSI [COD-LSI], a preprocessor LSI [PP-LSI], and a motion estimation LSI [ME3-LSI]. Scalable architecture allows a cascadable configuration for higher picture quality and higher resolutions. The encoder LSI, which is the key to this chip set, employs advanced hybrid architecture with a 162 MHz media-processor core [D30V] and dedicated video processing hardware. It also has dual-communication-ports for a multi-chip configuration. With above architecture, a single encoder LSI can perform SDTV encoding, and only six chips can perform HDTV encoding.