Low Cost Efficient Architecture for H.264 Motion Estimation
Sebastián López, F. Tobajas, Valentin De Armas, J. L., Roberto Sarmiento · 2005
A low cost VLSI architecture to compute the motion vectors required by the H.264/AVC video coding standard is presented in this paper. The possibility of avoiding motion estimation modes together with a novel partial distortion elimination strategy have been successfully incorporated in the proposed architecture, providing important savings in the power dissipation. As result, the implementation of the architecture in a low cost commercial FPGA is outlined in this paper, showing characteristics such as a reduced area occupation and an appropriate range of operation frequencies that make the architecture suitable for portable multimedia devices.