Power-efficient FSM mapping in FPGAs through SEMB dormancy control
Arun Janarthanan, Anurag Tiwari, Karen A. Tomko · Conference proceedings · 2007
Controllers implemented as finite-state machines (FSMs) occupy a major portion of FPGA designs. These FSMs can be implemented on synchronous embedded memory blocks (SEMBs) in current FPGAs. This approach, in addition to reducing considerable amount of power, also has several implementation benefits. In this research, we propose to further minimize the power consumed by the FSMs that are mapped to the SEMBs. We present an algorithm that maps the FSM outputs across the SEMBs based on its transition probabilities and thereby maximizes the dormancy of the SEMBs. For a given FSM as a state transition table, the algorithm determines for each transition in the table, the combination of inputs, outputs and state bits which contribute to the dormant transitions of the SEMB. Further, we develop a flow to determine the net power saved by this approach by computing the power consumed in the enable control logic and report the power savings for a variety of microprocessor models and MCNC benchmark circuits. Experimental results show a reduction of 8% to 21% in power compared to the SEMB based FSM technique and that it consumes 30% to 74% less dynamic power compared to the traditional LUT/FF implementation.