Shared buffer memory switch for an ATM exchange
N. Endo, Takahiko Kozaki, Tomihisa Ohuchi, Hiroshi Kuwahara, S. Gohara · IEEE Transactions on Communications · 1993
An asynchronous transfer mode (ATM) switch architecture called a shared buffer memory switch whose output cell buffers are shared among all the output ports of the switch is proposed. Experimental measurements and a discussion about the traffic characteristics of the switch architecture are carried out to determine how much buffer memory will be reduced through buffer sharing under various traffic conditions and to roughly estimate how many buffers are needed for the switch to meet certain requirements. The resultant estimate shows that buffer sharing reduces the necessary buffer memory to less than 1/5 of what would otherwise be required, and the required buffer size is about 128 cells/output for a 32*32 switch when considering bursty traffic conditions. LSI implementation is also discussed to show that a 32*32 switch can be composed of about 12 chips mounted on one printed board.>