Highly concurrent reduced-complexity 2-D systolic array for discrete Fourier transform
Pramod Kumar Meher · IEEE Signal Processing Letters · 2006
A simple two-dimensional (2-D) architecture is derived for highly concurrent systolization of the discrete Fourier transform (DFT). The concurrency of computation has been enhanced, and complexity is minimized by the proposed algorithm where an N-point DFT is computed via four inner-products of real-valued data of length ap(N/2). The proposed structure offers significantly lower latency, higher throughput, and involves nearly half the minimum of the area-time complexity of the existing multiplier-based DFT structures. It is found that the 2-D DFT using proposed one-dimensional (1-D) structure has nearly half the area-complexity and less than one-fourth of area-time complexity of the existing structures. Besides, it is also found to have nearly half the area-time complexity of the existing multiplierless DFT structure. Unlike some of the existing structures, the proposed one can be used for the DFT of any transform-length and does not involve tag-bit control