A variation-aware constant-order optimization scheme utilizing delay detectors to search for fastest paths on FPGAS
Kazutoshi Kobayashi, Y. Kume, C.L. Ngo, Yuta Sugihara, Hidetoshi Onodera · 2008
We propose a variation-aware post-fabrication optimization scheme on FPGAs. Variation-aware optimization usually takes huge measurement cost. The proposed scheme achieves a constant optimization cost for any circuit configuration. We utilize delay detectors embedded in clustered CLBs to choose fastest paths among multiple candidates. The delay detectors enable simultaneous measurement of critical path candidates to partition all critical paths into segments. The number of measurement to choose fastest paths on all critical paths does not depends on configurations but on FPGA architectures. We confirm that a simple heuristic algorithm can find the order of measurement near the lowest bound of the measurement cost and it is almost constant regardless of circuit configurations.