Hardware efficient logarithmic digital decimation filter
SHAILESH B. NERURKAR, Khalid H. Abed · 2005
In this paper, we use multidigit multidimensional logarithmic number system (MDLNS) to implement hardware efficient decimation filter architecture for communication receiver applications. We have considered single, two and three dimensional two-digit MDLNS architectures with a few nonbinary bases. The new MDLNS based digital filter, has advantages of 50% reduced read only memory (ROM) array and an optimal real nonbinary base, which reduces the overall hardware requirements. The proposed two-digit 2D logarithmic decimation filter achieves the required stop-band attenuation with considerable reductions in hardware compared to conventional decimation filter architectures. The proposed 2D architecture requires sixteen 3-bit adders, one 8-bit ROM and an 8-bit shifter for each filter coefficient, whereas conventional filter architecture needs 13-bit multipliers for each coefficient