Parallel coprocessor for Kohonen's self-organizing neural network
Jukka P. P. Saarinen, M. Lindroos, Jouni Tomberg, Kimmo K. Kaski · 2003
A new efficient integrated circuit implementation of the Self-Organising Feature Map algorithm is described. The fully digital hardware is designed for high speed parallel processing and modular expandability. The hardware implementation acts as a neural coprocessor which uses synchronous, bit-serial arithmetic. It includes functional units which perform the Euclidean distance computation, the minimum distance search, the memory controlling, and the updating function. The on-chip learning facilitates fully autonomous operation.>