A quantitative approach to benchmarking programmable logic architectures
J. Sturges · 2002
Describes a set of metrics based on analytical methods which evaluate the efficiency of programmable logic architectures, whether programmable logic device (PLD), programmable logic array (PLA), field-programmable gate array (FPGA), or complex channeled PLD (CPLD). The metrics are easily derived and form an equable measure of architectural efficiency across any device. Further, the metrics provide a pragmatic approach to device selection by quantifying the demands of a circuit, and comparing this against the availability of resources within a programmable architecture. In addition, the author provides a tutorial on the use of the metrics while focusing on a quantitative approach to benchmarking.>