A Generic Building Block For Hopfield Neural Networks With On-chip Learning
Michael K. Gschwind, Valentina Salapura, Oliver Maischberger · 2005
We present an extendable digital architecture for the implementation of a Hofield neural network using fieldprogrammable gate arrays (FPGAs). Due to its bit-serialk implementation, the actual digital circuitry is simple and highly regular, thus allowing efficient space usage of FPGAs. We exploit the reprogrammability of these devices to support on-chip learning. 1 Introduction This paper discusses a hardware implementation of a Hopfield neural network with on-chip learning using FPGAs. In the past, neural networks were often simulated on general purpose computing machines, which led to less-than-satisfying performance. Several ASIC implementations have been proposed [LM93] [LL93], but using FPGAs, specialized nets can be designed when only a few implementations are needed. In our past research, we have concentrated mainly on implementations based on off-chip learning. While onchip learning is a nice feature, we have felt that it is not really mission critical when much of a net's life...