A 58-µW single-chip sensor node processor using synchronous MAC protocol
Takashi Takeuchi, Shintaro Izumi, Takashi Matsuda, Hyeokjong Lee, Otake Yu, Toshihiro Konishi, Koh Tsuruda, Yasuharu Sakai, Hidehiro Fujiwara, Chikara Ohta, Hiroshi Kawaguchi, Masahiko Yoshimoto · 2009
We propose a single-chip ultralow-power sensor node processor with a synchronous media access control (MAC). It is comprised of a transceiver, i8051 micro processor, and dedicated MAC processor. The test chip occupies 3 × 3 mm2 in a 180-nm CMOS process, including 1.38 M transistors. The power is 58.0 µW under a network environment.